Joel Hruska’s article over at Extremetech doesn’t account for a number of considerations in AMD’s operating model and contractual obligations with its suppliers. The publicly available data related to the Zen 2 architecture with its chiplet and controller paradigm certainly yields the benefits noted by Hruska in a multi-chiplet design such as what is common for current-generation Threadripper and EPYC processors. While he does properly identify the candidate for the controller chip, he neglects to recognize that AMD still has a contractual obligation with GlobalFoundries due to the wafer supply agreement.
Furthermore, Economics 101 teaches us that the per-unit cost of manufacturing a “widget” is modified by scale; manufacturing more of the “glue” for AMD chiplet-based solutions will benefit AMD’s bill of materials. The AdoredTV video, which is certainly worthwhile to view regardless of however many grains of salt the presented information requires, does provide a realistic concept that isn’t far fetched. Not every central controller chip is going to meet the specs for providing the maximum number of memory channels for use. Repurposing lesser silicon for the mainstream line will make better use of the outputs from Globalfoundries while strengthening the potential performance capabilities for the Ryzen 3000-series product line.
The proposition related to AMD’s willingness to pay penalties for wafers produced at competing fabs may indeed be part of the long game. This would make more sense if and when a sub-12nm design is required for power, performance, or logical specifications for the controller. Incurring this financial penalty prior to the actual need for an advanced manufacturing process would be irresponsible of AMD from a cost optimization perspective.
Moving back to the transition from Ryzen 2000-series processors and associated clock speeds, Hruska’s skepticism on potential base and boost clocks for the proposed product lineup appears to neglect the benefits of TSMC’s 7nm manufacturing process along with further optimizations of the individual chiplet design that may have been achieved by AMD. Moving from 14nm in Zen to 12nm in Zen+ provided a 200-400Mhz improvement on average. In the chiplet model, each individual “processing” chiplet is theoretically less encumbered due to core functionality being offloaded to the dedicated central controller. 7nm process + central controller = more headroom for base and boost clocks.
The only part of Hruska’s article that’s at least grounded in reality is the recognition of bandwidth starvation for an integrated GPU. We’ve put the Ryzen 5 2400G through its paces and found it to be a very competent performer at 720p, yet started requiring turning down settings at 900p and 1080p to achieve a playable frame rate. The power draw and cost of HBM2 doesn’t make this approach viable at the proposed price points. The move to Navi will certainly have benefits from the performance and power consumption space but will most likely remain a solid choice for 2D and eSports titles. While the speeds and number of Navi compute units for applicable Ryzen 3000-series processors may be slightly lower than what has been shared via the rumor mill, I’d suggest buckling up and preparing to be razzle dazzled when Dr. Lisa Su speaks at CES!